a. Field of the Invention
The present invention relates to a synchronous signal generating system intended to generate a synchronous signal which is synchronous with a certain signal contained in a composite signal consisting of a plurality of signals, and more particularly it pertains to such a system including, as its main part, the so-called "phase-locked loop circuit."
B. Description of the Prior Art
There are many cases in the electronics industries wherein it is required to obtain a synchronous signal which is exactly synchronized with a certain signal contained in a composite signal consisting of plurality of signals with different frequencies. As an example of such cases, description will hereunder be made of the production of an FM-stereo broadcast.
Modern FM-stereo broadcasting is conducted by a suppressed carrier AM-FM modulation system which is called a pilot-tone system which in turn is a modification of the suppressed carrier modulation system. FM-stereo receivers for receiving such an FM-stero broadcast and reproducing the stereophonic sounds are designed so that the broadcast wave received is FM-demodulated by an FM-detector into a composite signal consisting of a main-channel signal, a sub-channel signal and a pilot signal (19kHz), and this composite signal is then demodulated or separated by a stereo demodulator into audio signals of the left and the right channels.
The stereo demodulator mentioned above is adapted to receive a carrier wave (38kHz) in addition to the main- and the sub-channel signals, for the demodulation of the composite signal. This carrier wave, which must be exactly synchronized with the sub-carrier wave (38kHz) used for the modulation of the sub-channel signal (the differential signal of the left- and the right-channel audio signals) conducted at the broadcasting station, is generated in the receiver and based on the pilot signal (19kHz) received for the sake of the generation of the carrier wave in the receiver.
In some conventional FM-stereo receivers, the so-called "phase-locked loop circuit" is provided for generating a carrier wave. The phase-locked loop circuit, in principle, comprises a voltage-controlled oscillator (VCO) which is capable of controlling the oscillation frequency by the control voltage applied thereto, and a phase detecting circuit which receives the composite signal containing the pilot signal (19kHz) and the output signal derived from the VCO and which thereby delivers a DC voltage having a magnitude proportional to the phase difference between the pilot signal and the output signal of the VCO, which DC voltage is applied, as the control signal, to the VCO so that the output signal of the VCO is synchronized (locked) with the pilot signal. Thus, at the output terminal of the VCO is obtained a synchronous signal which is synchronous with the pilot signal. In general, the phase-locked loop circuit further comprises a frequency divider and is arranged so that the output of the VCO is applied via the frequency divider to the phase detecting circuit for allowing the output signal of the VCO to be used, as it is, as the carrier wave (38kHz) having a frequency just twice that of the pilot signal (19kHz).
In FIG. 1 is shown an example of a synchronous signal (carrier wave) generating system according to the prior art, which includes a phase-locked loop circuit 1 and a lock-detecting circuit 8.
The phase-locked loop circuit comprises: a phase detecting circuit consisting of a phase detector 2 and a low-pass filter 3 assigned for filtering the output signal of the phase detector 2; a DC-amplifier 4 for amplifying the DC-voltage derived from the low-pass filter 3; a voltage-controlled oscillator 5 designed to oscillate at a frequency nearly four times the frequency of the pilot signal (19kHz) of the composite signal applied to the input terminal IN; and frequency dividers 6 and 7 through which the output of the voltage-controlled oscillator 4 is fed back to the phase detector 2. By the DC-amplifier's output which corresponds to the DC-voltage derived from the low-pass filter 3 of the phase detecting circuit, the oscillation frequency or the phase of the voltage-controlled oscillator 5 is controlled in such a manner that the phase difference between the pilot signal and the output signal of the frequency divider 7 both applied to the phase detector 2 is kept at 90.degree.. Thus, at the output terminal of the frequency divider 6 is derived a synchronous signal of a constant amplitude which is synchronous with the pilot signal and which is of a frequency exactly twice the frequency of the pilot signal. That is, the output signal of the frequency divider 6 can be used as the carrier wave for the demodulation of the composite signal into the left- and the right-channel audio signals.
With the prior art arrangement of the phase-locked loop circuit 1 mentioned above, however, if the levels of the main- and the sub-channel signals of the composite signal are excessively high, these signal components leak, after passing through the low-pass filter 3 and the DC-amplifier 4, to the voltage-controlled oscillator 5, so that the oscillation frequency of the voltage-controlled oscillator is caused to adversely fluctuate by these leaking signal components. This results in a poor stability of the phase of the synchronous signal generated at the output OUT. It should be noted therefore that, for the purpose of preventing such undesirable phase-fluctuation, the permissible level of the composite signal inputted to the phase-locked loop circuit 1 has in the past been kept at a considerably narrow range and also the capture frequency range of the phase-locked loop circuit 1 has been limited within a narrow range.
Referring again to FIG. 1, the lock-detecting circuit 8 is provided in order to indicate, on an indicator 13, whether the phase-locked loop circuit 1 is in the locked state or in the unlocked state. This circuit 8 includes a synchronous detector circuit consisting of a phase detector 9 and a low-pass filter 10, a DC-amplifier 11, and a frequency divider 12. When the phase-locked loop circuit 1 is in the state of being locked with the pilot signal of the composite signal, the frequency divider 12 receives from the frequency divider 6 a signal having a frequency exactly twice the frequency of the pilot signal, and then delivers to the phase detector 9 a signal having the same frequency as that of the pilot signal and being in phase with the pilot signal of the composite signal. As a result, a DC voltage of a magnitude proportional to the level of the pilot signal applied to the phase detector 9 is delivered from the low-pass filter and it is inputted to the DC-amplifier, and thus the indicator 13 is lit up by the output of the DC-amplifier 11. In the unlocked state of the phase-locked loop circuit 1, since the output of the frequency divider 12 is out of phase with the pilot signal and since no DC-voltage is delivered from the synchronous detector circuit, the indicator 13 is turned off.